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Read e-book online Embedded Processor-Based Self-Test PDF

By Dimitris Gizopoulos

ISBN-10: 1402028016

ISBN-13: 9781402028014

ISBN-10: 1441952527

ISBN-13: 9781441952523

Embedded Processor-Based Self-Test is a consultant to self-testing ideas for embedded processors. Embedded processors are usually used this present day in so much System-on-Chips (SoCs). trying out of microprocessors and embedded processors has constantly been a problem simply because most standard trying out recommendations fail whilst utilized to them. this is often a result of complicated sequential constitution of processor architectures, which is composed of excessive functionality datapath devices and complex regulate common sense for functionality optimization. dependent Design-for-Testability (DfT) and hardware-based self-testing options, which typically have a non-trivial effect on a circuit’s functionality, measurement and tool, can't be utilized with no critical attention and cautious incorporation into the processor design.

Embedded Processor-Based Self-Test exhibits how the strong embedded performance that processors supply can be used as a self-testing source. via a dialogue of alternative suggestions the booklet emphasizes at the rising zone of Software-Based Self-Testing (SBST). SBST relies at the concept of execution of embedded software program courses to accomplish self-testing of the processor itself and its surrounding blocks within the SoC. SBST is a inexpensive approach when it comes to overhead (area, velocity, power), improvement attempt and try software price, because it is utilized utilizing reasonably cheap, low-speed try out equipment.

Embedded Processor-Based Self-Test can be utilized through designers, DfT engineers, try out practitioners, researchers and scholars engaged on electronic trying out, and particularly processor and SoC try. This publication units the framework for comparisons between diverse SBST methodologies by way of discussing key specifications. It offers profitable purposes of SBST to a few embedded processors of other complexities and guide set architectures.

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Lower production volumes do not justifY very high testing costs and the extra problems analyzed above paved the way to the self-testing (or built-in selftesting - BIST) technology which is now well-respected and widely applied in modem electronic devices as it overcomes several of the bottlenecks of external, ATE-based testing. Development of effective self-testing methodologies has always been achallenging task, but it is now much more challenging than in the past because of the complexity of the electronic designs to which it is expected to be applied successfully.

For such hard-to-test designs, sufficient fault coverage can't be obtained unless serious Designfor-Testability changes are applied to the circuit. Design-for-Testability (DfT) refers to design modifications that help test patterns to be easier applied to the circuit's intern al nodes and node values to be easier observed at the circuit outputs. DfT modifications are not always easily adopted by circuit designers and incorporated in the chip. The ultimate target of test generation is to obtain a high fault coverage with an as small as possible test set (to reduce test application time - discussed right after) with minimum DfT changes in the circuit.

The time that an IC spends during testing under the control of an external tester adds to its total manufacturing time and final cost. Only high-end, expensive ATE of our days consisting of a huge number of channels, and a very high capacity memory for test patterns and test responses storage, and operating in very high frequencies, are capable to face the testing requirements of modem complex SoC architectures. When a complex chip design has to be tested by an external ATE with test patterns generated by ATPG tools and possibly applied in a scan-based fashion, several factors must be taken under serious considerations.

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Embedded Processor-Based Self-Test by Dimitris Gizopoulos


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